Of all the tasks an integrated circuit (IC) designer faces, resolving timing violations, especially in large, complex IC designs, is one of the most onerous. This task is made difficult, in part, by the fact that IC logic gate delays can vary up to three times in response to changes in power supply voltage, operating temperature, and variations in the IC manufacturing process. Of these three variables, variations in process tend to dominate over changes in voltage and temperature, primarily because changes in the IC process for a particular IC remain constant once that IC has been manufactured. Voltage and temperature, on the other hand are changeable and, to a certain degree, controllable while the IC is operating.
The variations associated with IC process tend to affect a single IC in a more or less uniform manner, so relative differences in speed between multiple logic gates residing on a single IC are not particularly sensitive to those changes. However, input and output signals that couple the IC with other electronic circuits are especially susceptible to IC process variations, as an off-chip circuit with which the IC communicates is not likely to possess the same process variation as the IC. As a result, the relative changes in signal propagation times between the IC and other external circuits tend to be much greater than that between two internal signals of the IC. Such problems are often exacerbated in designs that involve multiple clock domains, in which multiple clocks of different frequencies and phases are utilized.
Currently, a couple of automatic techniques are often employed by IC designers to limit the effects of IC process variations to avoid signal timing problems. For example, an analog phase-locked loop (PLL) or a digital delay-locked loop (DLL) is often used to synchronize IC clock signals with external clock sources to counteract the negative effects of IC process variation. In other situations, process-voltage-temperature (PVT) compensated input/output (I/O) pads for ICs have been utilized to combat the problem. However, circumstances often occur where neither of these techniques is available for a particular IC design, or the techniques cannot fully compensate for exceptional process variations.
Therefore, from the foregoing, a need currently exists for an alternative circuit or method that addresses the inherent problems associated with the manufacturing process variations of an integrated circuit.